(1) Field of the Invention
The present invention relates to a method of fabricating a metal oxide semiconductor field effect transistor, (MOSFET), device, and more specifically methods used to improve the packing density of MOSFET devices by forming a metal contact to a polysilicon gate structure via the use of a contact extension.
(2) Description of Prior Art
The semiconductor industry is continually striving to increase the performance of semiconductor chips, while still maintaining, or even decreasing, the cost of the higher performing silicon chip. These objectives have been achieved via micro-miniaturazation, or the ability to create silicon chips with sub-micron features. The sub-micron features allow the performance objective to be realized by resulting in silicon devices exhibiting less parasitic capacitances and resistances, then counterparts fabricated with less aggressive groundrules. In addition the use of sub-micron features allow a greater number of smaller chips to be produced from a specific size starting wafer, thus reducing the cost of an individual chip. The attainment of micro-miniaturazation, or the use of sub-micron features, has occurred mainly as a result of advances in specific semiconductor fabrication disciplines, such as photolithograhy and reactive ion etching. For example the use of more sophisticated exposure cameras, as well as the development of more sensitive photoresist materials, have allowed sub-micron images to be routinely obtained in photoresist layers. In addition the use of more advanced dry etching equipment and processes, have resulted in the successful transfer of the sub-micron images in overlying photoresist layers, to underlying materials, used for the fabrication of advanced semiconductor chips.
The increased density of silicon devices, resulting from the use of sub-micron features, brings about specific silicon chip design changes, needed to achieve the objective of increased device packing density. For example contacts to a polysilicon gate electrode, of a MOSFET device, can no longer be made near the MOSFET channel region, due to a lack of available area. Therefore MOSFET designs are now being used in which the contact to a polysilicon gate structure, or word line, is made in a region of the chip, away from the MOSFET channel region. However the process of creating a polysilicon contact extension, has to be designed to still satisfy the performance criteria, as well as designed not to sacrifice yield and reliability objectives. Bartholomew, et al, in U.S. Pat. No. 4,341,009, describe a process of using a thin layer of polysilicon to contact a source and drain region of a MOSFET device, with the contact to the polysilicon being made over a thick field oxide region, away from the channel region. This invention will describe a process for using a polysilicon contact extension, for a polysilicon word line, in which the yield of the polysilicon contact extension, and the performance of the polysilicon contact extension, in terms of contact resistance, have been successfully addressed.